The present invention relates generally to integrated circuit (IC) packages with bump type contacts. More particularly, the invention relates to miniature chip scale packages manufactured in wafer form and improved package interconnect structures for absorbing stresses introduced to the bumps after the package is attached to an external substrate, for example.
Currently, in order to remain competitive in the IC industry, IC process engineers continuously strive to reduce the overall size and corresponding cost of IC devices. As a result of this trend toward smaller overall sizes, sizes of individual features of the IC device and package have decreased and circuit density has correspondingly increased. That is, many IC engineers pursue ways to significantly increase the feature density so as to take full advantage of significant decreases in feature size and thereby reduce the overall size of the IC package. Additionally, so as to take full advantage of these significant increases in feature density, IC engineers seek to increase the I/O pin density of IC packages. With these goals in mind, IC chip engineers have developed a wide variety of package designs to maximize I/O pin density and reduce overall package size.
One example of a package design that has a relatively high I/O density is the flip chip type package. The typical flip chip package includes an array of pads to provide interconnections between the IC devices within the die and other electrical components or IC devices external to the die. An array configuration allows the engineer to utilize the package area for I/O pad placement, as opposed to other package designs, such as surface mount packages, which typically provide I/O pins only around the package periphery.
Another example of a package design with a relatively high I/O density is the chip scale package (CSP). The typical CSP has overall package dimensions substantially equal to that of the silicon active device or die that is enclosed within the package. One such type of CSP is manufactured in wafer form and hence referred to as a wafer level CSP or WLCSP. A surface mount die is a WLCSP in which I/O contacts are in bump form and located on the active side of the die.
FIG. 1A is a diagrammatic side view of a conventional flip chip package 100. The flip chip 100 includes a die 102 that typically has a plurality of conventionally fabricated IC device structures (not shown). These IC device structures may include, for example, transistors and interconnect layers. The die 102 has a top surface 108 that includes under bump pads (not shown). Contact bumps 106 are formed on the under bump pads of the top most surface 108. This top surface 108 is opposite a bottom surface 104 of the die 102. The bottom surface 104 is conventionally left bare, or exposed. That is, the bottom surface 104 is typically bare silicon.
A plurality of flip chip packages 101 are typically formed on the surface of a wafer (not shown). After the plurality of flip chip packages are formed on the wafer, each flip chip package is separated from the wafer in a dicing or singulation procedure.
After each flip chip is singulated from the wafer, a flip chip package (e.g., 100) may be inverted and carefully placed onto a portion of an substrate. Each contact bump (e.g., 106) of the flip chip package (e.g., 100) is then electrically coupled to an associated board contact (not shown) of the substrate. As shown, after the contact bump 106 is electrically coupled to the board contact of the substrate, an underfill layer is injected between the substrate and flip chip package 100 and around the contact bump 106 of the flip chip package 100. This underfill layer is required to reduce stresses that are introduced to the contact bump 106 and to improve reliability of the flip chip package 100.
FIG. 1B is a diagrammatic side view of a conductive pad and contact bump region of a conventional flip chip package 101 that is attached to a PCB. FIG. 1B, of course, represents only a portion of the entire flip chip package 101, which package includes a plurality of conductive pads, associated under bump pads, and associated contact bumps. As shown, the flip chip package portion 101 typically includes a die 102, a conductive pad 110, a passivation layer 112, an under bump pad 114, and a contact bump 106. The conductive pad 110 is patterned over the die 102, and the passivation layer 112 is formed over portions of the conductive pad 110 and die 102. The under bump pad 114 is formed over portions of the passivation layer 112 and conductive pad 110. The contact bump 106 is then grown onto the under bump pad 114.
Although conventional flip chip packages provide a means for achieving high density of I/O pads within a small package area, conventional flip chip packages have a few disadvantages. For example, stresses introduced on the contact bump may damage the flip chip package. When the flip chip package's contact bumps are coupled with the PCB's pads, the die of the flip chip package typically has a substantially different coefficient of thermal expansion (CTE) than the PCB. This difference in CTE's causes the die and the PCB to expand and contract at different rates and to pull and push on the contact bumps package and results in deformation and stresses of the contact bumps. These stresses may ultimately result in damage to the flip chip package, such as solder joint fatigue. By way of another stress related problem, stresses introduced at the contact bump may cause the contact bump to push into the underlying layers that form the die and cause substantial craters within the die itself. Another problem that may occur as a result of stresses on the contact bump is that the contact bump may tear open.
To reduce the likelihood of such stress-related problems, an underfill is often required to minimize the CIE mismatch from the die 102 to the substrate 116 and, thus, to improve reliability of the package. Unfortunately, the formation of this underfill layer (e.g., 115) results in an extra process step and an expenditure of man-hours and associated costs for the conventional flip chip package.
Another disadvantage of conventional flip chip packages is chipping during the dicing operation. Chipping is a problem for flip chip packages since the typically exposed bottom surface often fails to provide sufficient mechanical protection under certain stress conditions introduced during singulation. The exposed bottom surface also fails to provide protection from electrostatic shock or light induced bias for flip chip applications. That is, the packages may have functional problems due to photogenerated carriers when the bottom surface (e.g., 104) of the die (e.g., 102) is exposed to light, or the packages may be subject to an undesirable electrostatic shock during handling of the package subsequent to the dicing operation.
The aforementioned problems all contribute to an increase in production cost or a decrease in production yield. Consequently, there is a need for an improved IC package that provides a solution to the aforementioned problems and provides a plurality of contact bumps. Additionally, there is a need for a method for making such an improved package.